A Digital Power Amplifier in 28 nm CMOS for LTE Applications
This book shows the development of a power amplifier for LTE at the edge of planar CMOS technology. It includes theoretical design concepts, simulations and measurements for a power amplifier based on uplink specifications for mobile communication defined by 3GPP. It proofs the basic capability of C...
保存先:
| 第一著者: | |
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| フォーマット: | Online |
| 言語: | 英語 |
| 出版事項: |
FAU University Press
2025
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| 主題: | |
| オンライン･アクセス: | ONIX_20251215T160010_9783944057958_14 |
| タグ: |
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| 要約: | This book shows the development of a power amplifier for LTE at the edge of planar CMOS technology. It includes theoretical design concepts, simulations and measurements for a power amplifier based on uplink specifications for mobile communication defined by 3GPP. It proofs the basic capability of CMOS technology for a full integration on a SoC. Different power amplifier classes and linearization concepts are summarized and compared. A special focus is given on a selection of published watt-level power amplifiers as well as implemented DPAs. These basic considerations were the foundation for the later implemented designs. A stand-alone linear power amplifier was developed and characterized as a bare bumped die on a PCB. The DPA was integrated into an LTE transceiver what gave the possibility of on-chip verification of the entire system. Die pictures of the linear PA and the DPA show their architectures, which are implemented on-chip in 28nm CMOS technology, from the top metal layer perspective. |
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