Imaxe de Portada

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with...

Descrición completa

Gardado en:
Main Authors: Kundu, Santanu, Chattopadhyay, Santanu
Formato: Online
Idioma:inglés
Publicado: Taylor & Francis 2025
Subjects:
Power Consumption
NoC Architecture
Interconnection Networks in NoC
Architecture Design of Network – on- Chip
Swap Sequence
Evolution of NoC Architectures
Complete Binary Tree
Application Mapping on NoC
NoC Design
Reconfigurable Network-on-Chip Design
Bisection Width
Router Design for NoC
ILP Formulation
Signal Integrity Issues in NoC
Clock Gating
NoC Testing
Head Flit
Reconfigurable Computing
Node Degree
3-D NoC Architecture
Router Positions
3-D Integration
NoC Topology
thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and components
thema EDItEUR::U Computing and Information Technology::UB Information technology: general topics
thema EDItEUR::U Computing and Information Technology::UY Computer science
thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THR Electrical engineering
Acceso en liña:ONIX_20250512_9781466565272_62
Tags: Engadir etiqueta
Sen Etiquetas, Sexa o primeiro en etiquetar este rexistro!

Internet

ONIX_20250512_9781466565272_62

Títulos similares