Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with...
में बचाया:
| मुख्य लेखकों: | , |
|---|---|
| स्वरूप: | Online |
| भाषा: | अंग्रेज़ी |
| प्रकाशित: |
Taylor & Francis
2025
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| विषय: | |
| ऑनलाइन पहुंच: | ONIX_20250512_9781466565272_62 |
| टैग: |
कोई टैग नहीं, इस रिकॉर्ड को टैग करने वाले पहले व्यक्ति बनें!
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| _version_ | 1869522195881918464 |
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| author | Kundu, Santanu Chattopadhyay, Santanu |
| author_browse | Chattopadhyay, Santanu Kundu, Santanu |
| author_facet | Kundu, Santanu Chattopadhyay, Santanu |
| author_sort | Kundu, Santanu |
| collection | Directory of Open Access Books |
| description | Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems. |
| format | Online |
| id | doab-20.500.12854ir-159234 |
| institution | Directory of Open Access Books |
| language | eng |
| publishDate | 2025 |
| publishDateRange | 2025 |
| publishDateSort | 2025 |
| publisher | Taylor & Francis |
| publisherStr | Taylor & Francis |
| record_format | ojs |
| spelling | doab-20.500.12854ir-1592342025-05-16T05:13:35Z Network-on-Chip Kundu, Santanu Chattopadhyay, Santanu Power Consumption NoC Architecture Interconnection Networks in NoC Architecture Design of Network – on- Chip Swap Sequence Evolution of NoC Architectures Complete Binary Tree Application Mapping on NoC NoC Design Reconfigurable Network-on-Chip Design Bisection Width Router Design for NoC ILP Formulation Signal Integrity Issues in NoC Clock Gating NoC Testing Head Flit Reconfigurable Computing Node Degree 3-D NoC Architecture Router Positions 3-D Integration NoC Topology thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and components thema EDItEUR::U Computing and Information Technology::UB Information technology: general topics thema EDItEUR::U Computing and Information Technology::UY Computer science thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THR Electrical engineering Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems. 2025-05-13T04:04:05Z 2025-05-13T04:04:05Z 2025-05-12T09:36:17Z 2018 book ONIX_20250512_9781466565272_62 https://library.oapen.org/handle/20.500.12657/101522 9781466565272 9781138749351 9781466565265 9781315216072 9781351831963 9781351823272 https://directory.doabooks.org/handle/20.500.12854/159234 eng open access image/jpeg Attribution-NonCommercial-NoDerivatives 4.0 International https://library.oapen.org/bitstream/20.500.12657/101522/1/9781466565272.pdf Taylor & Francis CRC Press 10.1201/9781315216072 10.1201/9781315216072 fa69b019-f4ee-4979-8d42-c6b6c476b5f0 9781466565272 9781138749351 9781466565265 9781315216072 9781351831963 9781351823272 CRC Press 388 open access |
| spellingShingle | Power Consumption NoC Architecture Interconnection Networks in NoC Architecture Design of Network – on- Chip Swap Sequence Evolution of NoC Architectures Complete Binary Tree Application Mapping on NoC NoC Design Reconfigurable Network-on-Chip Design Bisection Width Router Design for NoC ILP Formulation Signal Integrity Issues in NoC Clock Gating NoC Testing Head Flit Reconfigurable Computing Node Degree 3-D NoC Architecture Router Positions 3-D Integration NoC Topology thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and components thema EDItEUR::U Computing and Information Technology::UB Information technology: general topics thema EDItEUR::U Computing and Information Technology::UY Computer science thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THR Electrical engineering Kundu, Santanu Chattopadhyay, Santanu Network-on-Chip |
| title | Network-on-Chip |
| title_full | Network-on-Chip |
| title_fullStr | Network-on-Chip |
| title_full_unstemmed | Network-on-Chip |
| title_short | Network-on-Chip |
| title_sort | network on chip |
| topic | Power Consumption NoC Architecture Interconnection Networks in NoC Architecture Design of Network – on- Chip Swap Sequence Evolution of NoC Architectures Complete Binary Tree Application Mapping on NoC NoC Design Reconfigurable Network-on-Chip Design Bisection Width Router Design for NoC ILP Formulation Signal Integrity Issues in NoC Clock Gating NoC Testing Head Flit Reconfigurable Computing Node Degree 3-D NoC Architecture Router Positions 3-D Integration NoC Topology thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and components thema EDItEUR::U Computing and Information Technology::UB Information technology: general topics thema EDItEUR::U Computing and Information Technology::UY Computer science thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THR Electrical engineering |
| topic_facet | Power Consumption NoC Architecture Interconnection Networks in NoC Architecture Design of Network – on- Chip Swap Sequence Evolution of NoC Architectures Complete Binary Tree Application Mapping on NoC NoC Design Reconfigurable Network-on-Chip Design Bisection Width Router Design for NoC ILP Formulation Signal Integrity Issues in NoC Clock Gating NoC Testing Head Flit Reconfigurable Computing Node Degree 3-D NoC Architecture Router Positions 3-D Integration NoC Topology thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and components thema EDItEUR::U Computing and Information Technology::UB Information technology: general topics thema EDItEUR::U Computing and Information Technology::UY Computer science thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THR Electrical engineering |
| url | ONIX_20250512_9781466565272_62 |
| work_keys_str_mv | AT kundusantanu networkonchip AT chattopadhyaysantanu networkonchip |